14. Coprocessor 0

14.30 ERET Instruction

Format: ERET

Description:

ERET is the R10000 instruction for returning from an interrupt, exception, or error trap. Unlike a branch or jump instruction, ERET does not execute the next instruction.

ERET must not itself be placed in a branch delay slot.

If the processor is servicing an error trap (SR2 = 1), then load the PC from the ErrorEPC and clear the ERL bit of the Status register (SR2). Otherwise (SR2 = 0), load the PC from the EPC, and clear the EXL bit of the Status register (SR1).

An ERET executed between a LL and SC also causes the SC to fail.

If there is no exception (EXL=0 and ERL=0 in the Status register), execution of an ERET instruction is meaningless.

Execution of an ERET when ERL=0, regardless of the state of EXL, sets EXL to 0 and a jump is taken to the address presently held in the EPC register, even when there is no exception.

Operation:

Exceptions:

Coprocessor unusable exception